We are looking for a RTL Engineer (mid-senior level) to join our client’s engineering team in Brașov. This role focuses on digital hardware design (ASIC/FPGA) and offers the opportunity to work on challenging projects in the semiconductors industry.

Key Responsibilities

• Understand design requirements, microarchitecture, and system architecture for IP and system solutions.
• Implement functional blocks in Verilog according to design and architecture specifications.
• Collaborate with design and verification engineers to support new features.
• Debug test failures, identify root causes, and work with verification/emulation engineers to resolve design defects.

Requirements

• Bachelor’s or Master’s degree in Computer, Electronics, or Electrical Engineering.
• Relevant experience in IP design (ASIC/FPGA).
• Knowledge of Ethernet protocols and IEEE 802.3 standards (MAC/PCS/PMA, PTP, FEC, flow control).
• Familiarity with interfaces like AXI streaming, AXI4-Lite, and connectivity protocols.
• Hands-on experience in timing closure for complex designs.
• Proficiency in debugging RTL code using simulation tools.
• Good working knowledge of SystemVerilog.
• Experience with ASIC tools (Primetime, Design Compiler) and code coverage/LINT (nice to have).
• Scripting experience (Perl, Python, Makefile, shell).
• Strong analytical, problem-solving, and communication skills; team-oriented mindset.

Location & Work Schedule

• 📍 On-site, Brașov
• Full-time position
• B2B Contract